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| HUDSON 2.0 Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction (FEC) device supporting the Digital Wrapper transmission standards for OTU1, OTU2, ODU1, ODU2, OPU1, and OPU2 as specified in G.709. The Hudson implements Performance Monitoring and overhead processing functions on the Digital Wrapper overhead bytes. In addition, the device contains SONET/SDH Performance Monitoring to verify the validity of the SONET/SDH OC-192 client data. The device can operate from a low rate of 6.25 MHz to a high rate of 693.483 MHz. Data entering and leaving the chip can be optionally deframed and framed, descrambled and scrambled, and decoded and encoded with forward error correction information. * Core logic runs on a 1.8 V power supply to reduce power consumption and LVCMOS I/O are 3.3 V compatible. * Two independent 16-bit parallel LVDS input and output ports at up to 693.483 MHz (11.096 Gbps). * Datapath options: Configurable as two completely independent data stream for full duplex operation. Configurable as a single data stream for regenerator operation with dual redundant I/O for optional protection switching. Either input port can be directly connected to either output port for loopback testing or bypass operation. * Supports SONET OC-192 Performance Monitoring at the input of the encoder side and at the output of the decoder side. * Supports G.709 "Interfaces for the optical transport network (OTN)" standard including specified frame structure, all overhead monitoring and processing, Maintenance signals, synchronous and asynchronous mapping and demapping. * ON/OFF control of Reed-Solomon (255,239) FEC Encoding/ Decoding and error correction. * Support for System test and diagnostics: internal BER generator, PRBS pattern generator and pattern analyzer for bit error rate testing capability. * Four programmable integer clock dividers to simplify clock generation. * Support for signal aggregation to higher rates via chip synchronization feature. * General Purpose Processor Interface: Gluess interface to MPC860, 25 MHz to 50 MHz bus speed. Also compatible with Intel microprocessor bus via Busmode selector. * Low power: 0.18 micron CMOS technology. Applications * * * * * 10 Gigabit Digital Wrapper Performance Monitor and Framer Protocol Independent DWDM Metropolitan Area Networks Optical Cross-connects OC-192 Port interface Fiber optic terminators, repeaters, and test equipment Figure 1: Block Diagram H u d s o n 2 .0 D EC _IN _S E L[1 :0] D U P_ O U T _S E L[1:0] D e c o d e (D E C ) S id e P a tte rn A n a ly z e r IN P U T _ P O R T _S W A P 0 D E C O D E IN [1 5 :0 ] D E C R X C LK D EC 1 :8 Demux O U T P U T _ PO R T _ S W AP 00 1 10 01 DEC OH F ram er 01 0 0,10 01, 11 FEC D ec o d e r 11 00 R a te M a tch F IF O DEC OH In s & S c ra m b le r D EC SONET PM 00 10 0 1 DUPO U T 1 :8 Mux D U P L E X O U T [1 5 :0 ] D UPTXC LK_OU T D E C R X C L K _ D IV C lo c k D iv id e r C lo c k D iv id e r DEC O H M o n /D ro p Sync B u ffe r D E C _ IN S C L K D E C _ IN S _ F P D E C _ IN S _S F P D E C IN S [7 :0 ] D E C _ IN S _ E N D U P T X C LK _ D IV R X_OH _CLK R X _ O H _ D A T A [7 :0 ] DRO PFP D ROP SFP E N C _D R P C L K E N C _ D R P [7 :0 ] ENC _DRP _FP EN C_DR P_SFP 1 D U P L E X IN [1 5:0 ] D UPR XCLK D U P IN 1 :8 Demux 0 DUP O H F ra m e r ENC SON ET PM O CH D e s c ra m & S C /O H M o n/D ro p 0 0, 01 1 00 10 0 01 1 0 0 IN P U T _P O R T _S W A P R a te M a tc h F IF O D U P R X C L K _ D IV C lo c k D iv id e r P a tte rn G e n e ra to r 1 E N C _IN _ SE L EN C O H F ra m e G en & FEC Encoder 10 O U T P U T _P O R T _S W A P EN C 8 :1 M ux E N C D A T A O U T [1 5 :0 ] EN CTXC LK PA T _G E N _ O N EN C O H Add TX_OH _CLK IN S F P T X _ O IN_ D A T A [7 :0] H SSFP T X _ O H _ IN S E N C _O U T _ SE L [1:0] C lo c k D iv id e r E N C T X C L K _ D IV E n co d e (E N C ) S id e FINAL/PRODUCTION RELEASE Information - The information contained in this document is about a product in its fully tested and characterized phase. All features described herein are supported. Contact AMCC for updates to this document and the latest product status. Empowering Intelligent Optical Networks HUDSON 2.0 Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 General Description Operating Frequencies Digital Wrapper functionality is available on the Hudson without regard to the actual data rate. The table below shows the supported frequencies of operation for Digital Wrapper transponder and SONET/SDH monitoring applications. Note that SONET/SDH monitoring is only supported for the OC-192 rate. Mode Digital Wrapper SONET/ SDH Monitoring Frequency (Data Rate) 6.25 MHz (100 Mbps) to 693.483 MHz (11.096 Gbps)1 622.08 MHz (9.95 Gbps) ONLY exists after decoding and deframing, to verify the integrity of the wrapper's SONET payload before it exits the Hudson. Wrapper overhead insertion and extraction, encoding and decoding, and performance monitoring are carried out on the output and input data streams respectively. The Hudson also contains many features to help the user with device integration and line testing. The Hudson high speed I/O is also compatible with the AMCC SONET/SDH Mapper or Interleaver/Disinterleaver. A typical edge application is shown below. Typical Single-line Application The following figures also illustrate a typical network application for the Hudson supporting a single data stream with dual redundant input and output lines. This configuration is useful for core transponder applications where it is desired to correct errors and do performance monitoring and output a corrected and FEC encoded data stream with or without new Optical Channel Overhead (Digital Wrapper OH) bytes. Data is received from the fiber and passed through a Clock/Data Recovery device (CDR) and a demultiplexer device to the Hudson. The Hudson optionally carries out SONET/ SDH monitoring, digital wrapper performance monitoring, error checking, and overhead data extraction and insertion. Detected errors and accumulated error counts can be accessed by the user either through a processor interface, an FPGA interface, or in a number of cases, from I/O pins. The data stream is then transmitted out onto the fiber via a high-speed multiplexer and an optics device. FEC decoding and encoding may be disabled individually. 1. Note: G.709 specifies exact rates for the Digital Wrapper. At the OTU2 rate, the frequency of the Hudson data ports is 669.33 MHz. The Hudson can be safely run at lower rates than specified in G.709 if compatibility to the standard is not required. Typical Full Duplex Application In the Full-Duplex configuration, the encode side and decode side of the Hudson can operate independently as shown below. At the input to the encode side of the Hudson is a SONET monitor which can verify the integrity of the SONET data stream prior to wrapping and FEC. At the output of the decode side, another SONET monitor Figure 2: Full-Duplex Configuration ORX DeMUX (S3092) ENCODER MUX (S3091) OTX Ring with NO FEC Coding S19203 FEC Coded Ring OTX MUX (S3091) DECODER DeMUX (S3092) ORX Figure 3: Typical Edge Application O P T IC S M ODULE S3092 S19203 GANGES / IN D U S C O N N E C T O R DEC S19202 / S19201 ENC S3091 FPG A U PROCESSOR 2 Empowering Intelligent Optical Networks HUDSON 2.0 Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 Figure 4: Dual-Redundant, SingleLline Configuration PRIM ARY ORX CDRand DeM UX (AM CC S3092) S19203 Decoder Encoder PRIM ARY M UX (AM CC S3091) OTX ORX CDR and DeM UX (AM CC S3092) SPARE M UX (AM CC S3091) SPARE OTX Figure 5: Se;f-Healing BLSR FEC Encoded Network S19203 From Network S3092 Decode In DEC ENC Encode Out To Network S3091 Duplex In Duplex Out Duplex Out To Network Duplex In From Network S3091 Encode Out ENC DEC S19203 Decode In S3092 AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (c) 2002 Applied Micro Circuits Corporation. All Rights Reserved. 200 Minuteman Road * Andover, MA 01810 * Tel: 978-247-8000 * Fax: 978-623-0024 * http:// www.amcc.comnical support, please call 800 840-6055 or email productsupport@amcc.com Empowering Intelligent Optical Networks 3 |
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